A synchronizer circuit synchronizing an input clock signal with a sampling clock signal to generate a synchronized signal, said synchronizer comprises: a sampling module sampling a logical value received on a first node at time points specified by one of a first edge type and a second edge type of said sampling clock signal and providing corresponding sampled values as said synchronized signal and an adaptive module generating said logical value at said first node, said adaptive module comprising: a first circuit inverting a logi. The negative edges in the input signal may also be processed similarly. The adaptive module causing the input to remain at logic high at least until the synchronization module provides logic level as the synchronized signal. The sampling module propagates the signal led at the input as the synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge in an input clock signal after a logic low corresponding to a prior negative edge is propagated to as a synchronized signal, and provides a logic high as an input to a sampling module. The adaptive module causing the input to remain at logic high at least until the synchroni.Ī synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal.
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